1. Field of the Invention
The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device having increased trap site density and a method of manufacturing the same.
2. Description of the Related Art
A unit memory cell of semiconductor memory devices, such as DRAM, includes one transistor and one capacitor. Therefore, to increase the integration density of a semiconductor memory device, the reduction of the volume of a transistor or the volume of a capacitor, or the volumes of both a transistor and a capacitor, is necessary.
In the case of the initial memory devices when the integration density of the semiconductor memory devices is not big issue, photography and etching processes could be performed with sufficient process margins. Therefore, the integration density of semiconductor memory devices could be increased by reducing the volumes of elements that constitute the semiconductor memory devices.
However, a new method, different from the conventional art, is required as the demand of semiconductor memory devices having high integration density increases.
The integration density of a semiconductor memory device is closely related to a design rule. Therefore, to increase the integration density of a semiconductor memory device, a strict design rule must be applied. In this case, the process margins of photolithography and etching processes can be significantly reduced. This denotes that the photolithography and etching processes must be performed more precisely.
When process margins of the photolithography and etching processes are reduced, a yield also can be reduced. Therefore, a method to increase the integration density of semiconductor memory devices without reducing the yield is needed.
To meet the requirements, many semiconductor memory devices having different structures from conventional semiconductor memory devices have introduced. The new semiconductor memory devices include a data storing medium that can store charges on an upper side of a transistor and has a data storing function different from a conventional capacitor.
A SONOS memory device is also one of a newly introduced semiconductor memory device. FIG. 1 is a cross-sectional view illustrating a conventional memory device.
Referring to FIG. 1, a source region 12 and a drain region 14 to which an n type conductive dopant is implanted on a p type semiconductor substrate 10 (hereinafter, semiconductor substrate) are formed. A channel region 16 is formed between the source 12 and the drain 14. Also, a gate stack 18 is formed on the channel region 16 of the semiconductor substrate 10. The gate stack 18 is composed of a tunneling oxide film 18a, a nitride film Si3N4 18b, a blocking oxide film 18c, and a gate electrode 18d. Here, the nitride film 18b has a trap site having predetermined density. Therefore, when a predetermined voltage is applied to the gate electrode 18d, electrons passed through the tunneling oxide film 18a are trapped in the trap site of the nitride film 18b. The blocking oxide film 18c blocks the migration of electrons to the gate electrode 18d while the electrons are trapped.
In the conventional semiconductor memory device, binary scale information can be stored and read using the characteristic of varying the threshold voltage between when electrons are trapped and when not trapped in the trap site of the nitride film 18b. 
Here, when the density of a trap site increases, more electrons can be trapped. Then, the variation of threshold voltage can be increased. That is, the density of the trap site can significantly affect the characteristics of a memory device. Conventionally, to increase the density of a trap site, techniques of scattering or depositing nano scale particle sizes, such as Si-nano particles, on a surface of a thin film have been developed. However, these methods have limits to increase the density of trap site per unit area. These methods have various technical problems, especially, the non-uniformity of particle size and particle distribution, to be applied to a flash memory.